AMD Zen 6 CPUs to Adopt "Sea-of-Wires" D2D Interconnect for Unmatched Power Efficiency & Latency Gains

Date: September 28, 2025 | By: Tech Editorial Team

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AMD Reinvents Die-to-Die Communication with Zen 6

AMD is preparing a groundbreaking shift in chip design with its next-generation Zen 6 CPUs. The company is moving away from its long-standing SERDES-based interconnect and introducing a "Sea-of-Wires" approach that promises massive improvements in power efficiency, latency, and bandwidth scalability.

This innovation isn’t just a theory — early evidence of the new D2D (die-to-die) interconnect has already been spotted in AMD Strix Halo APUs, confirming that Zen 6 CPUs will likely carry forward this revolutionary approach.

Why SERDES Was Holding Back Progress

For years, AMD relied on SERDES PHYs to handle die-to-die communication. While effective in the Zen 2 through Zen 5 era, this technology required data to be converted into high-speed serial streams and then reassembled on the other end. This process consumed significant energy and introduced latency overheads due to:

• Clock recovery
• Equalization
• Encoding/decoding steps

While this system was sufficient when CPUs had fewer specialized components, the rise of NPUs (Neural Processing Units), advanced AI accelerators, and memory bandwidth-hungry workloads has made the SERDES approach outdated.

The Sea-of-Wires: How Strix Halo Shows the Future of Zen 6

AMD’s upcoming Strix Halo APUs have already demonstrated how Zen 6 processors could handle D2D interconnect differently. Instead of serializing traffic, the company is now laying out hundreds of thin parallel wires directly beneath the dies.

This is achieved using TSMC’s InFO-oS (Integrated Fan-Out on Substrate) and a Redistribution Layer (RDL). These technologies enable AMD to build a dense, high-bandwidth wiring system beneath the chiplets, allowing direct parallel communication with lower power draw and minimal latency.

Key Benefits of the Sea-of-Wires Interconnect:

• Reduced Latency: Eliminates the delays caused by serializing/deserializing data streams.
• Improved Power Efficiency: Lowers energy costs since clock recovery and equalization steps are no longer required.
• Higher Bandwidth: Parallel wiring allows scalable communication paths for more demanding workloads.
• Future-Proofing: Supports AI, machine learning, and high-performance gaming requirements in next-gen CPUs.

Challenges of the Fan-Out Approach

While the Sea-of-Wires design brings tremendous advantages, it also introduces new engineering challenges. The multi-layer RDL complexity can make routing signals more difficult, and engineers must carefully manage the under-die space to ensure that the dense wiring doesn’t interfere with other components.

Despite these challenges, the benefits outweigh the hurdles, making this one of AMD’s most ambitious architectural evolutions since the introduction of chiplets.

How Zen 6 Will Shape the Future of CPUs

The Zen 6 CPU lineup is expected to push boundaries in AI computing, gaming, and enterprise workloads. With faster interconnects, AMD can ensure that CCDs, NPUs, and SoCs communicate seamlessly, paving the way for higher IPC gains, better multi-core scaling, and lower thermal output.

Industry experts believe that this “Sea-of-Wires” D2D innovation could give AMD an edge over Intel in next-gen architectures, especially as chiplet-based processors dominate the semiconductor landscape.

Conclusion: AMD’s Bold Step Toward the Future

AMD’s move from SERDES to Sea-of-Wires interconnect marks a significant leap in chiplet communication technology. By leveraging TSMC’s InFO-oS packaging and parallel wire architecture, AMD is preparing Zen 6 CPUs to deliver unmatched efficiency, speed, and scalability in the competitive processor market.

As the world gears up for more AI-driven and performance-intensive computing, AMD Zen 6’s interconnect breakthrough could be the defining factor that reshapes the CPU industry in 2026 and beyond.